1. Field of the Invention
This invention relates to an improved computing system and to parts thereof and relates particularly, but not exclusively, to such systems usable in multiple instruction multiple data (MIMD) applications.
2. Description of Prior Art
In this art there has been an increasing demand for more powerful computers. Such demand has been met by the development of single processors of steadily greater complexity using the fastest possible circuits. This approach has been successful to some extent only. Typical examples of computers using the current state of the art fast circuits are the machines known as C.D.C. STAR and CRAY-1. The approach taken to develop the fastest possible circuits has several disadvantages.
Firstly, there is a need to perform operations at a rate which exceeds the fastest possible speed at which the units can process arithmetic. This has meant that in order to provide for the necessary speed, several such units must be employed simultaneously. This, in turn, requires that there be a control unit capable of initiating the various functions in overlapped or simultaneous time sequences. This is extremely difficult, and the devices devised for this purpose have been extremely expensive.
Secondly, the need to employ the fastest available circuit technology has meant that the full economic benefits of large scale integration have not been exploited in the computers. Further, the complexity of the design of very large uni-processors means that they cannot readily be divided into function units of a size matching the available size of LSI chips without requiring an uneconomically large number of different functional unit types.
Thirdly, because the uni-processor is capable of executing only one program per se at a time, the use of a large uni-processor to execute a large number of tasks on a time sharing basis including interactive tasks requires a complex control unit.
Fourthly, the large uni-processor is designed and constructed as a specific unit. It is not possible to gradually increase the processor power to match a gradually increasing work load. Hence, very large uni-processors may spend the early part of their life seriously underused and the later part seriously overloaded.
In the art of implementing control units to control a series of uni-processors for dividing overlapping processing of information, there have been many serious problems. These have been identified as problems relating to the architectural nature of the system as a whole. The following ideas have been identified as specific problems:
1. Choice of interconnecting structure for the system bus.
2. Interrupt assignment strategy. PA1 3. Memory mapping techniques. PA1 4. Interprocessor communications. PA1 5. Task synchronization. PA1 (a) at least two processor devices PA1 (b) at least two memory devices PA1 (c) each said device having its own interface for interconnecting the respective device to a bus PA1 (d) a bus so interconnected with said device PA1 (e) a system clock; characterized in that, each transaction on the bus comprises process code addresses as well as a device code address, a transaction type control signal and a data signal all occurring simultaneously during a clock period, and in that all interfaces are arranged to simultaneously examine each bus transaction during the clock period, and in that the system can bind all devices for a particular process by a common process code so that there will be no interaction with devices bound to different process in the system.
These difficulties have been documented in an article entitled "Analysis of Multiple--Microprocessor System Architecture", by A. J. Weissberger, pp. 151-162, Computer Design, June, 1977.
In addition, some of the problems associated with providing the required power of computers are attributable to the fact that additional processors and/or memory units cannot be added, at will, to the system to increase the power to the required level.